Raising · $3M seed

Wafer-scale metalens arrays for AI data center co-packaged optics (CPO)

Upgrade the collimation layer. Keep the proven fiber-array platform.

OneOQ designs flat nano-optics on fused silica for the collimation and coupling layer inside fiber arrays, built for the 1310 nm O-band and for optical interconnect and optical I/O in silicon photonics.

  • 1310 & 1550 nmO-band and C-band design
  • Q1 2027Samples targeted
  • 20M / yrVolume target
Scanning electron microscope image of a metalens array: nanopillars on fused silica arranged in circular unit cells
Problem

Fiber attach is the bottleneck in co-packaged optics for the AI data center

Demand keeps climbing

Hyperscale AI data center bandwidth and power demand keep rising, and optical interconnect is moving closer to the chip.

Fiber attach limits scale

In co-packaged optics (CPO) and near-package optics, the density, alignment and cost of the fiber array interface become first-order constraints for optical I/O.

Collimation has to be precise

Multi-channel fiber arrays need every channel collimated accurately at 1310 nm, across a whole array, at volume.

Solution

A metalens array in place of the refractive microlens layer

The metalens array (MLA) is a flat, lithographically defined nano-optics layer on fused silica. It drops into the collimation and coupling layer of a fiber array, so the fiber-array platform stays and only the collimation layer is upgraded for silicon photonics and co-packaged optics.

Wafer-scale metalens manufacturing Flat & thin optics Single-mask Dicing-friendly Nano-optic design freedom IP in progress
Light path

From diverging fiber mode to collimated beam at 1310 nm

PIC Fiber arrayMetalens arraySi-photonics chip divergingcollimated · 1310 nm
Spec snapshot

Engineering sample

SubstrateFused silica
Pitch0.100 to 0.500 mm range
FormatWafer or diced parts, in standard formats (e.g. 12.7 mm diced dies)
CoatingAR-coated
Design wavelength1310 nm (O-band) and 1550 nm band (C-band)
SamplesTargeted Q1 2027

Engineering-sample targets. Qualification data to follow.

Why now

Optical interconnect is moving next to the chip

AI data center scale-out

Growing hyperscale clusters multiply the number of optical links that have to be built and aligned.

CPO ramp

Co-packaged and near-package optics put the fiber array interface right beside the silicon photonics chip.

Manufacturable nano-optics

A flat, single-mask, dicing-friendly, wafer-scale metalens layer is built to scale like a semiconductor part.

Insights

CPO & optical I/O: tech, then market

A scroll through the OneOQ poster series, from the physics of fiber attach to where the optical interconnect market is heading.

Tech series19 posters

Density is the new bottleneck
Tech 01

Density is the new bottleneck

AI packages keep packing more compute into the same shoreline, so copper lanes hit density and loss walls at the package edge. Optical I/O raises bandwidth per millimeter of edge without the same SerDes tax, which is why density—not raw FLOPs—is becoming the constraint that matters.

Why CPO shortens the electrical hop
Tech 02

Why CPO shortens the electrical hop

Traditional pluggables force high-speed electrical signals across inches of PCB before light takes over. Co-packaged optics shrink that hop to millimeters next to the ASIC, cutting equalization power and freeing lane count to scale.

O-band 1310 nm for silicon-photonics fiber attach
Tech 04

O-band 1310 nm for silicon-photonics fiber attach

Inside datacenters, silicon photonics usually couples in the O-band near 1310 nm, where standard single-mode fiber has near-zero chromatic dispersion. That band choice drives fiber-attach design: mode field, collimation optics, and the tolerances you can hold in volume.

Detachable FAU vs permanently soldered optics
Tech 05

Detachable FAU vs permanently soldered optics

Permanent optical bonds can look simpler on day one, but they make every fiber or connector failure a package-level event. A detachable fiber-array unit keeps the optical path serviceable so ops can replace fiber without scrapping the whole engine.

Thermal / power density in AI packages
Tech 06

Thermal / power density in AI packages

Kilowatt-class accelerators put optics in a harsh thermal neighborhood where alignment and reliability still have to hold. CPO only works if the optical path stays stable while the silicon next door dumps heat.

Optical I/O growth as GPU clusters scale
Tech 07

Optical I/O growth as GPU clusters scale

Bigger training and inference clusters multiply links between GPUs, switches, and racks. Optical lane count scales with that fabric, so interconnect density has to grow as fast as the compute graph.

Packaging yield: why flat optics help volume
Tech 08

Packaging yield: why flat optics help volume

Discrete micro-optics are hard to place repeatably at the counts AI packages need. Flat, wafer-processed optics bring lithographic consistency to collimation and coupling, which is how you protect packaging yield at volume.

Hyperscaler rack-scale networking pressure
Tech 09

Hyperscaler rack-scale networking pressure

Hyperscale AI racks pack more bandwidth into fixed power, cooling, and faceplate budgets. That pressure pushes interconnect toward shorter electrical reaches and denser optical ports at the rack and package.

Energy per bit: optics inside the package
Tech 10

Energy per bit: optics inside the package

Moving the E/O conversion closer to the ASIC cuts the power burned in long electrical SerDes hops. At AI scale, picojoules per bit at the package edge are as strategic as FLOPs per watt on the die.

Pluggable vs co-packaged: when each wins
Tech 11

Pluggable vs co-packaged: when each wins

Pluggables win when you need field replaceability and flexible reach options. CPO wins when density and energy per bit dominate—and many AI systems will mix both where each is strongest.

Fiber-array alignment tolerances that matter
Tech 12

Fiber-array alignment tolerances that matter

Multi-fiber attach lives or dies on micron-level lateral and angular alignment. Coupling loss stacks across the array, so the collimation layer has to be designed for the tolerance budget you can actually manufacture.

Reticle-scale metalens arrays for multi-fiber ports
Tech 13

Reticle-scale metalens arrays for multi-fiber ports

A fiber array needs a matching array of collimation elements, not one lens at a time. Reticle-scale metalens arrays print that pattern in one wafer process, sized to the port pitch of the FAU.

Hyperscaler AI training fabrics and optical lane count
Tech 14

Hyperscaler AI training fabrics and optical lane count

Large training fabrics add optical lanes at every hop—GPU to switch, leaf to spine, rack to rack. Lane count becomes a first-class architecture variable, not an afterthought of copper SI.

Serviceability: why detachable attach survives ops
Tech 15

Serviceability: why detachable attach survives ops

In production AI clusters, the expensive failure mode is replacing a whole optical engine for a fiber or connector fault. Detachable attach keeps optics maintainable so operators can service the link, not the package.

Glass vs silicon substrates for collimation layers
Tech 16

Glass vs silicon substrates for collimation layers

Glass offers broadband transparency and familiar optical CTE behavior for free-space coupling paths; silicon brings semiconductor process alignment but different thermal and transparency trade-offs. Collimation-layer substrate choice is a packaging decision as much as an optics one.

Near-package optics vs true CPO
Tech 17

Near-package optics vs true CPO

Near-package optics sit close to the ASIC but still off the main package substrate; true CPO co-packages the optical engine with the silicon. Where the engine sits changes reach, power, thermal load, and how dense the fiber attach can be.

Signal integrity limits of copper at 100G+ per lane
Tech 18

Signal integrity limits of copper at 100G+ per lane

At 100G+ per lane, copper loss, crosstalk, and equalization budgets shrink the usable electrical reach fast. That is the physics pushing high-radix AI systems to put optics earlier in the path.

Hyperscaler CapEx: fewer hops, denser optics
Tech 19

Hyperscaler CapEx: fewer hops, denser optics

Hyperscalers pay for every switch hop, cable, and watt in the fabric. Fewer electrical hops and denser optical ports cut network CapEx and OpEx even when the optical engines themselves look expensive on paper.

From MLA tooling to wafer-level nanostructure
Tech 20

From MLA tooling to wafer-level nanostructure

Classic microlens arrays lean on molding and discrete tooling that struggle at AI port counts. Wafer-level nanostructures move collimation into a semiconductor-like process so multi-fiber optics can scale with the package.

Market series10 posters

AI Datacenter CapEx: Interconnect Is a Growing Slice
Market M1

AI Datacenter CapEx: Interconnect Is a Growing Slice

AI datacenter budgets still go mostly to compute, but networking and optics take a bigger share as clusters grow. Every added accelerator brings more links, so interconnect grows into a strategic line item.

CPO & NPO: An Emerging Market Moves Toward Volume
Market M2

CPO & NPO: An Emerging Market Moves Toward Volume

Co-packaged and near-package optics are moving from pilots toward early deployments as AI systems hit electrical I/O limits. How fast they reach volume depends on packaging maturity, serviceability, and supply-chain readiness as much as on the physics.

AI Is Expanding the Optical I/O Market
Market M3

AI Is Expanding the Optical I/O Market

Optical interconnect grew up serving telecom and then cloud, and AI clusters are now its fastest-growing frontier. Each new tier of demand needs more bandwidth per link and many more links.

Hyperscaler Networking: More Bandwidth, Same Power Budget
Market M4

Hyperscaler Networking: More Bandwidth, Same Power Budget

Hyperscale operators keep needing more bandwidth while their power, cooling, and space budgets stay roughly fixed. That squeeze favors interconnect that delivers more bits per watt and per unit of faceplate.

Where System Value Sits: Switch Silicon + Optical Engines
Market M5

Where System Value Sits: Switch Silicon + Optical Engines

In a co-packaged switch, value is shared between the switch ASIC and the optical engines around it. As optics move into the package, more of the system's value and engineering moves to the package edge.

Fiber Attach Scales With Every Optical Package
Market M6

Fiber Attach Scales With Every Optical Package

Every optical engine needs a precise, reliable fiber connection, so attach volume grows with each package shipped. Fiber attach that is manufacturable and serviceable at scale becomes a market in its own right.

Bandwidth Density Is a Market Driver
Market M7

Bandwidth Density Is a Market Driver

Bandwidth per millimeter of package edge isn't just an engineering metric. It sets how far an AI system can scale, so the technologies that raise density decide where market value goes.

The OpEx of Copper at Scale
Market M8

The OpEx of Copper at Scale

Electrical SerDes power looks small per link, but across a fleet of many thousands of links it becomes a real operating cost. Cutting energy per bit with optical I/O lowers the bill for power and cooling over the system's life.

Optics Packaging Capacity: A Supply-Chain Question
Market M9

Optics Packaging Capacity: A Supply-Chain Question

The path from wafer to photonics, packaging, fiber attach, and finished system runs across a global supply chain. Packaging and attach capacity may limit how fast optical interconnect can scale, as much as demand does.

From Pluggables to Co-Packaged: A Gradual Share Shift
Market M10

From Pluggables to Co-Packaged: A Gradual Share Shift

Pluggable transceivers remain the workhorse today, and co-packaged optics are expected to take share gradually where density and power matter most. Both will coexist for years, and the mix is likely to shift step by step, not all at once.

Team & contact

Talk to OneOQ

Hossein Alisafaee, PhD

Founder & CEO, OneOQ LLC

Team of five: one full-time and four part-time.

ceo@oneoq.com
oneoq.com
Fishers, Indiana

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